1. Technical Field
Embodiments of the present disclosure generally relate to semiconductor packages and, more particularly, to semiconductor packages including molded stacked die with terrace-like edges.
2. Related Art
In the electronics industry, a single unified package including a plurality of semiconductor dies or a plurality of semiconductor chips is increasingly in demand with the development of faster, large-capacity, miniaturized semiconductor packages. If the single unified packages are employed in electronic systems, sizes of the electronic systems may be reduced and lengths of signal transmission paths in the electronic systems may also be reduced. In the event that the single unified package includes a plurality of semiconductor dies therein, a portion of the plurality of semiconductor dies may be exposed at a surface of the single, unified package in order to effectively dissipate heat from the semiconductor dies through the single unified package.
When at least two semiconductor packages are combined with each other to realize a high-level semiconductor package such as a system-in-package (SIP), a stack structure of a plurality of semiconductor dies may be required to provide a portion of the SIP. In such a case, the stack structure of the plurality of semiconductor dies may be realized without any printed circuit board (PCB), and a portion of the stack structure of the plurality of semiconductor dies may be exposed at a surface of the SIP.
If a portion of a semiconductor die is exposed at a surface of a semiconductor package, an external shock applied to the exposed portion of the semiconductor die or a physical contact with an external member may cause mechanical damage such as chipping defects. The chipping defects may generate particles that may cause an additional failure. Accordingly, a stack structure of semiconductor dies for suppressing the chipping may be required to realize the high-level semiconductor package such as the SIP.